1. Technical Field
The present invention relates to a method for calibrating a transmission line pulse (TLP) test system.
2. Background Art
Different on-wafer ESD test equipments are available today: TLP, vfTLP, HBM, and MM ESD tests. During such ESD stress tests, one wants to characterize the voltage and current waveforms through the device under test (DUT), during such an ESD stress. The known available measurement techniques do not result in V and I waveforms measured at the DUT level, however, as they will always include system parasitics like probe resistances and inductances, lossy transmission line interconnects etc.
Consequently, TLP type of measurements are only used for quasi static characterization of ESD clamps. There is a growing interest to study also the I and V transients during a TLP stress, because of the availability of an on-wafer TLP tester in any ESD test lab. Up to now, the only methodology with which this can be attained is disclosed in Trémouilles, D. et al., “Transient Voltage Overshoot in TLP testing—Real or Artifact?”, EOSESD symposium 2005. This methodology needed RF characterization of the connection line and the probe parasitics, which is user unfriendly as it requires additional costly RF test equipment.